1. Field of the Invention
The present invention relates to a frame number detecting device used in digital data playback devices, specifically an optical disk playback device etc. to detect frame numbers in the playback data.
2. Description of the Background Art
When a digital data playback device such as an optical disk playback device plays back data, it first reads a playback signal from a recording medium such as an optical disk by using a detecting portion such as an optical pickup. The read playback signal is amplified in an amplifier, waveform-corrected in a waveform equalizer and converted into a digital signal. Then a synchronization detecting circuit detects a frame sync signal contained in the playback signal to establish synchronization with the playback data.
In DVDs (Digital Versatile Discs) which are now attracting attention as new information media, data such as image data etc. is recorded in frames as shown in FIG. 11 and a group of frames form a sector. One sector contains 26 frames, each frame containing a 32-bit frame sync signal (eight kinds SY0 to SY7) and 1456-bit data
Each of the frame sync signals SY0 to SY7 is a signal composed of a 13-bit bit pattern and a 19-bit bit pattern coupled together, the 13-bit bit patterns are unique respectively to the eight kinds and the 19-bit bit pattern called 14T4T is common to SY0 to SY7. In practice, the frame sync signals SY0 to SY7 each have four kinds of variations, so that they have a total of 32 kinds of bit patterns.
As shown in FIG. 11, the frame sync signals SY0 to SY7 are respectively assigned to the 26 frames in one sector according to a predetermined arrangement. The frame sync signal located at the beginning of the sector is particularly called a sector sync signal. Herein, the bit pattern types of the frame sync signals SY0 to SY7 are referred to as sync signal types and the numbers showing positions of the frame sync signals counted from the beginning of the sector are referred to as sync numbers.
The sync number can be specified by observing the variation in the sync signal type (for example, when the sync signal type has changed from SY0 to SY5, it can be specified that it has changed from SY0 of the 0th frame to SY5 of the 1st frame). The frame sync signals SY0 to SY7 thus function as frame number information for specifying the frame numbers within the sector.
DVD requires detecting the frame sync signal and detecting and securing the sector sync signal. Particularly, in order to detect and secure the sector sync signal, it is extremely important to correctly detect where the playback frame is located in the sector and provide it as an output. However, it is actually difficult to correctly detect the frame number because of presence of defects on the disk (dirt, scratches, fingerprints, etc.) and resulting data bit slip etc. (the bit slip means detection error of the playback signal caused by a defect such as dirt, scratch, etc. on the disk, which leads to loss of synchronization between clock and data). For example, when actually playing back an optical disk such as a DVD, the quantity of light input to the optical pickup varies because of irregularities on the transparent resin package covering the disk, fingerprints on its surface, etc. The analog signal processing portion then may erroneously detect a 3T pattern (a data string of 1, 0, 0) as a 2T pattern (a data string of 1, 0) during digitization. Such a detection error of course occurs also when reading the sync signal type. Therefore various frame number detecting devices have been suggested to correctly detect the frame number.
FIG. 12 is a block diagram showing part of the device shown in FIG. 7 in Japanese Patent Application Laid-Open No. 10-55627 (1998) as an example of such a frame number detecting device. In this diagram, the reference character 1 denotes an S/P (serial→parallel) converting portion for converting serial data into parallel data, 4 denotes a sync signal type detecting/encoding portion for detecting the sync signal type of the frame sync signal in the parallel data and encoding the sync signal type, 5a denotes a latch circuit for latching the sync signal type detected and encoded, 6 denotes a sync number encoding portion for encoding the sync number (i.e. frame No.) on the basis of the variation between successive sync signal types, 7 denotes a frame counter which counts up in accordance with sync signal input and outputs its count number as an expected frame number and which changes its count number to the output value provided from the sync number encoding portion 6 under a given condition, 8 denotes a comparator portion for comparing the sync number outputted from the sync number encoding portion 6 and the count number from the frame counter 7, 9 denotes a state detecting counter which counts up/down a state variable as an indicator of the correctness of the frame number detection in accordance with the result provided from the comparator portion 8, 10a denotes a gate circuit composed of a combination of AND and OR gates etc., for detecting that the state variable of the state detecting counter 9 has reached its lowest value, and 11 denotes a gate circuit for setting the condition under which the frame counter 7 changes its count number to the output value provided from the sync number encoding portion 6.
Next, operation of this frame number detecting device is described. First, the S/P converting portion 1 converts the digital input signal S0 as serial data into a plurality of pieces of parallel data S1 containing the same contents.
The sync signal type detecting/encoding portion 4 comprises a sync signal type detecting portion 4a and a sync signal type encoding portion 4b; in the sync signal type detecting portion 4a, the pieces of parallel data S1 are respectively supplied to detectors for detecting SY0 to SY7 to specify the sync signal type among SY0 to SY7. The detected sync signal type is encoded in the sync signal type encoding portion 4b. The encoded sync signal type information is outputted as a signal S2, which is held for one frame period in the latch circuit 5a. 
The sync number encoding portion 6 encodes the current frame number and outputs it as a signal S5 on the basis of the combination of the sync signal type information signal S2 and the signal S3 outputted from the latch circuit 5a. For example, when the signal has changed as SY3→SY7 (when the output signal S3 from the latch circuit 5a is SY3 and the sync signal type information signal S2 is SY7), it determines that the current frame number is the twenty-third frame as shown in FIG. 11. It then performs encoding to represent this frame number and outputs it as the signal S5.
When the sync signal type detecting/encoding portion 4 was unable to correctly detect the sync signal type and the combination of the signal S2 representing the encoded sync signal type information and the output signal S3 from the latch circuit 5a does not correspond to any existing frame number (for example, when the sync signal type has changed from SY4 to SY3, i.e. when the output signal S3 of the latch circuit 5a is SY4 and the sync signal type signal S2 is SY3), the sync number encoding portion 6 determines that the frame number cannot be specified and causes its output signal S4 to go Low.
The frame counter 7 increments its count number in response to an enable signal (input to the terminal E) which corresponds to the sync signal input and outputs this value as a signal S7 from the terminal Q (when its count number has reached 25, it returns to 0). However, when a given condition was satisfied and the signal S6 inputted to the terminal L has become High, it loads the signal S5 from the terminal IN and changes the count value to the output value provided from the sync number encoding portion 6.
The comparator portion 8 compares the output signal S5 from the sync number encoding portion 6 and the output signal S7 from the frame counter 7 to see whether they agree with each other. The result of comparison is outputted as a signal S8 to the state detecting counter 9 which is constructed as a 2-bit up/down counter (the “2-bit” means that it can take values 0, 1, 2 and 3: these values are referred to as “state variable” in this application). When the two match, the signal S8 causes the value of the state variable to go up, for example, and it is outputted as a signal S9 from the state detecting counter 9. On the other hand, when they mismatch, it causes the value of the state variable of the state detecting counter 9 to go down.
When the signal S9 outputted from the state detecting counter 9 is at its lowest level (when the signal S5 and the signal S7 have continuously disagreed, e.g. when the state variable value is 0), the gate circuit 10a causes the signal S10 to go High. This signal S10 is inputted together with the signal S4 to the gate circuit 11 constructed as an AND gate. When both of the signals S10 and S4 are High, the signal S6, i.e. the output of the gate circuit 11, goes High. This is the condition under which the frame counter 7 loads the signal S5 or the output from the sync number encoding portion 6.
This prevents the frame counter 7 from running by itself with its count number disagreeing with the output signal S5 from the sync number encoding portion 6. That is to say, the comparator portion 8 compares the output signal S5 provided from the sync number encoding portion 6 and the signal S7 as an expected frame number provided from the frame counter 7 and checks whether the two agree. When the frame counter 7 is running by itself with its count number disagreeing with the output signal S5 of the sync number encoding portion 6, the state detecting counter 9 detects it on the basis of the output from the comparator portion 8 and then it causes, through the gate circuit 10a and 11, the frame counter 7 to reflect the contents of the signal S5 outputted from the sync number encoding portion 6, so as to make a correction.
The use of the frame counter 7 makes it possible to output a correct frame number as its output signal S7 even when the sync signal type is not correctly detected because of defects on the disk (dirt, scratches, fingerprints, etc.)
FIG. 13 is a timing chart showing the operation of the frame number detecting device shown in FIG. 12. This timing chart shows an example in which the sync signal type was erroneously detected as SY4 in the frame S3i where it should be SY7 and the sync signal type was correctly detected as SY3 in the next frame. When it thus changes from SY4 to SY3 (when the signal S3 is SY4 and the signal S2 is SY3), the sync number encoding portion 6 cannot specify the frame number since this variation does not correspond to any existing frame number, so that it cannot output the signal S5 as shown in the frame S5o. It changes the output signal S4 from High to Low.
In this case, since the input signal S6 to the terminal L is not High, the frame counter 7 increments its count number from 21 to 22 in response to the enable signal corresponding to the sync signal input and outputs this value as the signal S7 (it is assumed that the count number was 21 in the preceding frame). Further, since the signals S5 and S7 disagree, the comparator portion 8 outputs the signal S8 to cause the state variable of the state detecting counter 9 to go down from 1 to 0 (it is assumed that the value of the state variable was 1 in the preceding frame). FIG. 13 shows this value of the signal S9 or the state variable in the frame S9i. 
Now, when the next frame data is inputted and its sync signal type is correctly detected as SY7 (when the signal S3 is SY3 and the signal S2 is SY7), the sync number encoding portion 6 outputs the frame number 23 corresponding to this variation as the signal S5. It also changes the output signal S4 from Low to High since it was able to specify the frame number.
Since the state variable in the state detecting counter 9 was 0 in the preceding frame and the sync number encoding portion 6 was able to specify the frame number, the output signal S6 from the gate circuit 11 goes High. The frame counter 7 therefore loads the signal S5 from the terminal IN and changes the value of its count number to the output value of the sync number encoding portion 6. That is to say, as shown in the frame S7j in FIG. 13, the count number of the frame counter 7 takes the value 23.
At this time, since the signal S5 and the signal S7 agree with each other, the comparator portion 8 provides the signal S8 to cause the state variable of the state detecting counter 9 to go up from 0 to 1.
In this way, the conventional frame number detecting device reads the frame number by using the frame counter 7 which runs by itself in response to an enable signal. Therefore, even if the sync signal type was unable to be correctly detected as shown in the frame S3i in FIG. 13 because of a defect on the disk (dirt, scratch, fingerprint, etc.), a correct frame number can be provided as the output signal S7 of the frame counter 7. The frame number can thus be more correctly outputted than in a device which specifies the frame number by directly using the sync signal type detected in the sync signal type detecting/encoding portion 4.
In FIG. 13, the signal S2 should be detected as SY4 in the frame S2a immediately following the frame in which SY7 was detected, since the frame number should be 24. However, SY2 is detected because of a detection error. As a result, despite the fact that it is actually the twenty-fourth frame, the sync number encoding portion 6 outputs the frame number as 20 as shown in the frame S5m in accordance with the combination of SY7→SY2 (the signal S3 is SY7 and the signal S2 is SY2). In this case, it keeps the output signal S4 High since it was able to specify the frame number.
Then, since the state variable of the state detecting counter 9 was 1 in the preceding frame, the output signal S6 from the gate circuit 11 goes Low and the frame counter 7 therefore increments the count number without loading the signal S5. That is to say, the count number of the frame counter 7 takes the value 24.
Since the signal S5 and the signal S7 disagree at this time, the comparator portion 8 provides the signal S8 to cause the state variable of the state detecting counter 9 to go down from 1 to 0 as shown in the frame S9h. 
Now, when the next frame data is inputted and its sync signal type is correctly detected as SY7 (when the signal S3 is SY2 and the signal S2 is SY7), the sync number encoding portion 6 detects the frame number on the basis of the erroneously detected SY2 in the frame S3h and outputs the frame number 21 corresponding to this variation as the signal S5 as shown in the frame S5n, in spite of the fact that the frame number should be 25. It keeps the output signal S4 High since it was able to specify the frame number.
At this time, since the state variable of the state detecting counter 9 was 0 in the preceding frame and the sync number encoding portion 6 was able to specify the frame number, the output signal S6 of the gate circuit 11 goes High. The frame counter 7 therefore loads the signal S5 from the terminal IN and changes the value of its count number to the output value provided from the sync number encoding portion 6. That is to say, the count number of the frame counter 7 takes the value 21 as shown in the frame S7g of FIG. 13. Needless to say, this value is wrong: it should actually be 25.
Also, since the signal S5 and the signal S7 agree at this time, the comparator portion 8 outputs the signal S8 to cause the state variable of the state detecting counter 9 to go up from 0 to 1.
Subsequently the next data frame is inputted, and if its sync signal type is correctly detected as SY0 (when the signal S3 is SY7 and the signal S2 is SY0), they operate as described above and the frame counter 7 increments the value of its count number from 21 to 22 as shown in the frame S7h and outputs it as the signal S7. This value is of course wrong: it should actually be 0.
Then the next frame data is inputted and if its sync signal type is correctly detected as SY5 (when the signal S3 is SY0 and the signal S2 is SY5), they operate as described above and the frame counter 7 loads the signal S5 as shown in the frame S7i and changes the value of its count number to the output value 1 provided from the sync number encoding portion 6.
In this way, in the conventional frame number detecting device, the frame counter 7 provides a wrong output when the sync signal type detecting/encoding portion 4 detects a wrong sync signal type because of a defect on the disk (dirt, scratch, fingerprint, etc.) and resulting bit slip etc. and if the sync signal type combination correspond to an existing frame number.